题解 | #不重叠序列检测#

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input data,
	output reg match,
	output reg not_match
	);
parameter S0=4'd0;
parameter S1=4'd1;
parameter S2=4'd2;
parameter S3=4'd3;
parameter S4=4'd4;
parameter S5=4'd5;

parameter M1=4'd6;
parameter M2=4'd7;
parameter M3=4'd8;
parameter M4=4'd9;
parameter M5=4'd10;

reg [3:0] state;
reg [3:0] next_state;
always@(posedge clk or negedge rst_n)
begin 
	if(!rst_n) state<=S0;
	else state<=next_state;
end

always@(state or data)
begin 
 case(state)
 S0:
 begin 
if(data==1'b0) next_state=S1;
else  next_state=M1;
 end
 S1:
  begin 
if(data==1'b0) next_state=M2;
else  next_state=S2;
 end
 S2:
  begin 
if(data==1'b0) next_state=M3;
else  next_state=S3;
 end
 S3:
  begin 
if(data==1'b0) next_state=M4;
else  next_state=S4;
 end
 S4:
  begin 
if(data==1'b0) next_state=S5;
else  next_state=M5;
 end
 S5:
  begin 
if(data==1'b0) next_state=S0;
else  next_state=S0;
 end
 M1:
  begin 
 next_state=M2;

 end
 M2:
  begin 
  next_state=M3;	
 end
 M3:
  begin 
  next_state=M4	;
 end
 M4:
  begin 
  next_state=M5;	
 end
 M5:
  begin 
 next_state=S0;	
 end
 default :next_state=S0;
 endcase
end


always@(posedge clk or negedge rst_n)
begin 
	if(!rst_n) begin match<=0; not_match<=0; end
	else 
	begin
     case(state)
 S0:
 begin 
match<=0; not_match<=0;
 end
 S1:
  begin 
match<=0; not_match<=0;
 end
 S2:
  begin 
match<=0; not_match<=0;
 end
 S3:
  begin 
match<=0; not_match<=0;
 end
 S4:
  begin 
match<=0; not_match<=0;
 end
 S5:
  begin 
if(data==0) begin  match<=1; not_match<=0; end
else begin match<=0; not_match<=1; end
 end
 M1:
  begin 
match<=0; not_match<=0;

 end
 M2:
  begin 
match<=0; not_match<=0;	
 end
 M3:
  begin 
match<=0; not_match<=0;	
 end
 M4:
  begin 
	match<=0; not_match<=0;
 end
 M5:
  begin 
match<=0; not_match<=1;	
 end
 default: begin match<=0; not_match<=0; end
 endcase
	end
end
endmodule