题解 | #占空比50%的奇数分频#

`timescale 1ns/1ns

module odo_div_or
   (
    input    wire  rst ,
    input    wire  clk_in,
    output   wire  clk_out7
    );

//*************code***********//
reg [2:0]cnt;
always@(posedge clk_in or negedge rst)
if(!rst)
cnt<=0;
else if(cnt==6)
cnt<=0;
else
cnt<=cnt+1;

reg clk1;
reg clk2;

always@(posedge clk_in or negedge rst)
if(!rst)
clk1<=0;
else if(cnt==3)
clk1<=1;
else if(cnt==6)
clk1<=0;
else
clk1<=clk1;

always@(negedge clk_in or negedge rst)
if(!rst)
clk2<=0;
else if(cnt==3)
clk2<=1;
else if(cnt==6)
clk2<=0;
else
clk2<=clk2;

assign clk_out7=clk1|clk2;
//*************code***********//
endmodule