题解 | #状态机-重叠序列检测#

`timescale 1ns/1ns

module sequence_test2(
	input wire clk  ,
	input wire rst  ,
	input wire data ,
	output reg flag
);
//*************code***********//
reg[4:0] state,next_state;
parameter IDLE=5'B00001,
S1=5'B00010,
S10=5'B00100,
S101=5'B01000,
S1011=5'B10000;

always@(posedge clk or negedge rst)
if(!rst)
	state<=IDLE;
else
	state<=next_state;

always@(*)
case(state)
IDLE:	next_state=data?S1:IDLE;
S1:		next_state=data?S1:S10;
S10:	next_state=data?S101:IDLE;
S101:	next_state=data?S1011:S10;
S1011:	next_state=data?S1:S10;   //到最后一个状态不回IDLE，继续监测
default:next_state=IDLE;
endcase

always@(posedge clk or negedge rst)
if(!rst)
	flag<=0;
else if(state==S1011)
	flag<=1;
else 
	flag<=0;


//*************code***********//
endmodule