题解 | #状态机与时钟分频#

`timescale 1ns/1ns

module huawei7(
	input wire clk  ,
	input wire rst  ,
	output reg clk_out
);

//*************code***********//
parameter A=1, B=2, C=3, D=4;
reg [2:0]state,nstate;
always@(posedge clk or negedge rst)begin
	if(!rst)
		state<=0;
	else
		state<=nstate;
end
always@(*)begin
	case(state)
		A:nstate<=B;
		B:nstate<=C;
		C:nstate<=D;
		D:nstate<=A;
		default:nstate<=A;


	endcase

end

always@(posedge clk or negedge rst)begin
	if(!rst)
		clk_out<=0;
	else if(nstate==A)
		clk_out<=1; 
	else
		clk_out<=0;
end



//*************code***********//
endmodule