题解 | #位拆分与运算#

`timescale 1ns/1ns

module data_cal(
input clk,
input rst,
input [15:0]d,
input [1:0]sel,

output [4:0]out,
output validout
);
//*************code***********//

reg[15:0]d_reg;
always@(posedge clk or negedge rst)begin
    if(!rst)begin
        d_reg<=0;
    end
    else begin
        if(sel==2'b0)begin
            d_reg<=d;
        end
        else begin
            d_reg<=d_reg;
        end
    end
end
      
assign out=sel[1]?(sel[0]?(d_reg[3:0]+d_reg[15:12]):(d_reg[3:0]+d_reg[11:8])):(sel[0]?(d_reg[3:0]+d_reg[7:4]):(0));
assign validout=((rst==0)|(sel==2'b0))?0:1;

//*************code***********//
endmodule