题解 | #数据串转并电路#

`timescale 1ns/1ns

module s_to_p(
	input 				clk 		,   
	input 				rst_n		,
	input				valid_a		,
	input	 			data_a		,
 
 	output	reg 		ready_a		,
 	output	reg			valid_b		,
	output  reg [5:0] 	data_b
);
reg[2:0]cnt;
reg[5:0]data;
always@(posedge clk or negedge rst_n)begin
	if(!rst_n)begin
		ready_a<=0;
	end
	else begin
		ready_a<=1;
	end
end
always@(posedge clk or negedge rst_n)begin
	if(!rst_n)begin
		cnt<=0;
	end
	else begin
		if(valid_a & ready_a)begin
			if(cnt<3'd5)begin
				cnt<=cnt+1;
			end
			else begin
				cnt<=0;
			end			
		end
		else begin
			if(cnt<3'd5)begin
				cnt<=cnt;
			end
			else begin
				cnt<=0;//防止cnt为5时，valid_a为0时还能一直输出
			end
				
			end
	end
end
always@(posedge clk or negedge rst_n)begin
	if(!rst_n)begin
		data<=0;
	end
	else begin
		if(valid_a&ready_a)begin
			data<={data_a,data[5:1]};
		end
		else begin
			data<=data;
		end
	end
end
always@(posedge clk or negedge rst_n)begin
	if(!rst_n)begin
		data_b<=0;
	end
	else begin
		if(cnt==3'd5 )begin
			data_b<={data_a,data[5:1]};
		end
		else begin
			data_b<=data_b;
		end
		
	end
end
always@(posedge clk or negedge rst_n)begin
	if(!rst_n)begin
		valid_b<=0;
	end
	else begin
		if(cnt==3'd5 &ready_a)begin
			valid_b<=1;
		end
		else begin
			valid_b<=0;
		end
	end
end

endmodule