题解 | #占空比50%的奇数分频#

`timescale 1ns/1ns

module odo_div_or
   (
    input    wire  rst ,
    input    wire  clk_in,
    output   wire  clk_out7
    );

//*************code***********//
reg clk_out7_reg;
reg [2:0]cnt;
always@(posedge clk_in or negedge rst or negedge clk_in)begin
    if(!rst)cnt<=0;
    else begin
        if(cnt==3'd6)cnt<=0;
        else cnt<=cnt+1;
    end
end
always@(posedge clk_in or negedge rst or negedge clk_in)begin
    if(!rst) clk_out7_reg<=0;
    else begin
        if(cnt==6)clk_out7_reg<=~clk_out7_reg;
        else clk_out7_reg<=clk_out7_reg;
    end
end
assign clk_out7=clk_out7_reg;

//*************code***********//
endmodule