题解 | #位拆分与运算#

`timescale 1ns/1ns

module data_cal(
input clk,
input rst,
input [15:0]d,
input [1:0]sel,

output [4:0]out,
output validout
);
//*************code***********//
    reg [15:0] out_reg;
    reg validout;
    reg [4:0] out;

    always@(posedge clk or negedge rst)
        begin
            if(!rst)
                begin
                    out_reg <= 5'd0;
                    validout <= 1'b0;
                    out <= 5'd0;
                end
            else 
                begin
                    case(sel)
                        2'd0:
                            begin
                               out_reg <= d;
                               validout <= 1'b0;
                               out <= 5'd0;
                            end
                        2'd1:
                            begin
                               out <= out_reg[3:0] + out_reg[7:4];
                               validout <= 1'b1; 
                            end
                        2'd2:
                            begin
                               out <= out_reg[3:0] + out_reg[11:8];
                               validout <= 1'b1; 
                            end
                        2'd3:
                            begin
                               out <= out_reg[3:0] + out_reg[15:12];
                               validout <= 1'b1; 
                            end
                    endcase
                end
        end

//*************code***********//
endmodule