题解 | #交通灯#

`timescale 1ns/1ns

module triffic_light
    (
		input rst_n, //异位复位信号，低电平有效
        input clk, //时钟信号
        input pass_request,
		output wire[7:0]clock,
        output reg red,
		output reg yellow,
		output reg green
    );
    reg[7:0]cnt0;
    reg[1:0]cs,ns;
    parameter Idle=0,Red=1,Yellow=2,Green=3;

    always@(posedge clk or negedge rst_n)begin
        if(!rst_n)cnt0<=8'd10;
        else if(cs==Idle & cnt0==8'd8)cnt0<=8'd10;
        else if(cs==Red & cnt0==8'd1)cnt0<=8'd5;
        else if(cs==Yellow & cnt0==8'd1)cnt0<=8'd60;
        else if(cs==Green & pass_request & cnt0>8'd10)cnt0<=8'd10;
        else if(cs==Green & cnt0==8'd1)cnt0<=8'd10;
        else cnt0<=cnt0-1;
    end

    always@(posedge clk or negedge rst_n)begin
        if(!rst_n)cs<=Idle;
        else cs<=ns;
    end
    always@(*)begin
        if(!rst_n)ns=Idle;
        else begin
            case(cs)
            Idle:begin
                if(cnt0==8'd8)ns=Red;
                else ns=ns;
            end
            Red:begin
                if(cnt0==8'd1)ns=Yellow;
                else ns=ns;
            end
            Yellow:begin
                if(cnt0==8'd1)ns=Green;
                else ns=ns;
            end
            Green:begin
                if(cnt0==8'd1)ns=Red;
                else ns=ns;
            end
            endcase
        end
    end
    always@(posedge clk or negedge rst_n)begin
        if(!rst_n)begin
            red<=0;
            yellow<=0;
            green<=0;
        end
        else begin
            case(ns)
            Idle:begin
                red<=0;
                yellow<=0;
                green<=0;
            end
            Red:begin
                red<=1;
                yellow<=0;
                green<=0;
            end
            Yellow:begin
                red<=0;
                yellow<=1;
                green<=0;
            end
            Green:begin
                red<=0;
                yellow<=0;
                green<=1;
            end
            endcase
        end
    end
    assign clock=cnt0;
endmodule