题解 | #非整数倍数据位宽转换24to128#

`timescale 1ns/1ns

module width_24to128(
	input 				clk 		,   
	input 				rst_n		,
	input				valid_in	,
	input	[23:0]		data_in		,
 
 	output	reg			valid_out	,
	output  reg [127:0]	data_out
);

reg [4-1  :0]   cnt			;
reg [120-1:0]	data_out_tmp;

always@(posedge clk, negedge rst_n) begin
	if(rst_n == 1'b0 || cnt == 15) cnt <= 0;
	else if(valid_in == 1'b1) cnt <= cnt + 1'b1;
end

always@(posedge clk, negedge rst_n) begin
	if(rst_n == 1'b0) data_out_tmp <= 0;
	else if( valid_in == 1'b1) begin
		if		(cnt <= 4) 	  			data_out_tmp[(120-1-cnt*24)		-: 24] 	<= data_in; //tarns1
		else if	(cnt >= 5 && cnt <= 9 ) data_out_tmp[(120-1-(cnt-5)*24)	-: 24] 	<= data_in; //trans2
		else if	(cnt >= 10 && cnt <=14) data_out_tmp[(120-1-(cnt-10)*24)-: 24] 	<= data_in; //trans2
	end
end

// the 2*8/24 always need to be output in high bit on data_out

always@(posedge clk, negedge rst_n) begin
	if(rst_n == 1'b0) data_out <= 0;
	else if( valid_in == 1'b1 ) begin
		if(cnt == 5 ) data_out <= {data_out_tmp				  		, data_in[24-1-:8 ]};
		if(cnt == 10) data_out <= {data_out_tmp[(120-1-8 ):0]		, data_in[24-1-:16]};
		if(cnt == 15) data_out <= {data_out_tmp[(120-1-16):0]		, data_in          };
		//else data_out <= 'b0 ;
	end
end

always@(posedge clk, negedge rst_n) begin
	if(rst_n == 1'b0 ) 							 valid_out <= 1'b0;
	else if(cnt == 5 || cnt == 10 || cnt == 15)  valid_out <= 1'b1;
	else 			   							 valid_out <= 1'b0;
end

endmodule

刚开始以为第六个24bit中只要8bit，后面发现这24 bit的每个8bit都要塞在后面的128bit数据中输出出去，所以对于每次的第六个24bit，第一次128 bit里用8bit，第二次用16bit，第三次用24bit，第四次和第一次一样，如此循环