题解 | #位拆分与运算#

`timescale 1ns/1ns

module data_cal(
input clk,
input rst,
input [15:0]d,
input [1:0]sel,

output reg [4:0]out,
output reg validout
);
reg [15:0]d1;
//*************code***********//
always@(posedge clk or negedge rst)begin
    if(!rst)begin
        out <= 0;
        validout <= 0;
        d1<=0;
    end
    else if(sel)begin
        validout <= 1;
        out <= (sel==1) ? (d1[3:0]+d1[7:4]) : 
               (sel==2  ? (d1[3:0]+d1[11:8]):
                           d1[3:0]+d1[15:12]);
    end
    else begin
        validout <= 0;
        out <= 0;
        d1<=d;////input valid only when sel == 0;
    end
end

//*************code***********//
endmodule