题解 | #移位运算与乘法#

`timescale 1ns/1ns
module multi_sel(
input [7:0]d ,
input clk,
input rst,
output reg input_grant,
output reg [10:0]out
);
//*************code***********//
reg [7:0] d_dly;
reg [3:0] cnt;
wire      rst_dly_catch;
reg       rst_dly;
assign rst_dly_catch = ~rst_dly & rst;    //抓取复位上升沿，拉高初始的input_grant。
always @(posedge clk or negedge rst)begin 
    if(!rst)begin
        d_dly <= 8'd0;
        rst_dly <= 1'b0;
      end
    else begin
        d_dly <= d;
        rst_dly <= rst;
    end
end
always @(posedge clk or negedge rst)begin //计数0->1，1->3,2->7,3->8
    if(!rst)
        cnt <= 4'd0;
    else if(cnt >= 4'd3)
        cnt <= 4'd0;
    else
        cnt <= cnt + 4'd1;
end
always @(posedge clk or negedge rst) begin  //输出out
    if(!rst)
        out <= 11'd0;
    else begin
     case(cnt)
        4'd0:out <= d;
        4'd1:out <= 3 * out;
        4'd2:out <= 7 * (out/3);
        4'd3:out <= 8 * (out/7);
        default:  ;
        endcase
    end
end
always @(posedge clk or negedge rst)begin //inpu_grant输出控制
    if(!rst)
        input_grant <= 1'b0;
    else if (rst_dly_catch == 1'b1)
        input_grant <= 1'b1;
    else if(cnt == 4'd0) 
        input_grant <= 1'b1;
    else
        input_grant <= 1'b0;
end
//*************code***********//
endmodule