题解 | #位拆分与运算#

`timescale 1ns/1ns

module data_cal(
input clk,
input rst,
input [15:0]d,
input [1:0]sel,

output reg [4:0]out,
output reg validout
);
//*************code***********//

reg [15:0] d_get;

always @(posedge clk, negedge rst) begin

    if(!rst)
        begin
           out = 0;
           validout = 0; 
        end
    else 
        begin
            case(sel)
                2'b00: 
                    begin
                        d_get = d;
                        out = 0;
                        validout = 0;
                    end
                2'b01:
                    begin
                        out = d_get[3:0] + d_get[7:4];
                        validout = 1;
                    end
                2'b10:
                    begin
                        out = d_get[3:0] + d_get[11:8];
                        validout = 1;
                    end
                2'b11:
                    begin
                        out = d_get[3:0] + d_get[15:12];
                        validout = 1;
                    end
            endcase
        end 
end
//*************code***********//
endmodule