题解 | #数据累加输出#

`timescale 1ns/1ns

module valid_ready(
	input 				clk 		,   
	input 				rst_n		,
	input		[7:0]	data_in		,
	input				valid_a		,
	input	 			ready_b		,
 
 	output		 		ready_a		,
 	output	reg			valid_b		,
	output  reg [9:0] 	data_out
);

reg [1:0]   cnt     ;
always@(posedge clk or negedge rst_n)begin
    if(!rst_n)begin
        cnt <= 2'b0;
    end
    else if(valid_a && ready_a)begin
        cnt <= cnt+1'b1;
    end
    else 
        cnt <= cnt;
end

always@(posedge clk or negedge rst_n)begin
    if(!rst_n)begin
        valid_b <= 1'b0;
    end
    else if(cnt == 2'd3 && valid_a && ready_a)begin
        valid_b <= 1'b1;
    end
    else if(valid_b && ready_b)
        valid_b <= 1'b0;
    else 
        valid_b <= valid_b;
end

assign ready_a = ~(valid_b && (~ready_b));

// reg [9:0]   data_out_temp       ;
always@(posedge clk or negedge rst_n)begin
    if(!rst_n)begin
        data_out <= 10'b0;
    end
    else if(cnt == 2'd0 && valid_a == 1'b1 && ready_b)begin
        data_out <= {{2{1'b0}},data_in};
    end
    else if(valid_a && ready_a)begin
        data_out <= data_out + data_in;
    end 
    else 
        data_out <= data_out;
end
endmodule

将所有触发条件都写入判断式中是最稳健的做法