题解 | #序列检测器（Moore型）#

`timescale 1ns/1ns

module det_moore(
   input                clk   ,
   input                rst_n ,
   input                din   ,
 
   output	reg         Y   
);

reg [1:0] cur_state,next_state;
parameter s1=0; parameter s2=1; parameter s3=2; parameter s4=3;

always@(posedge clk or negedge rst_n)
begin
    if(!rst_n)
        cur_state<=s1;
    else
        cur_state<=next_state;
end

always@(*)
begin
    if(!rst_n)
        next_state=s1;
    else
        case(cur_state)
            s1:begin
                if(din==0)
                    next_state=next_state;
                else
                    next_state=s2;
            end
            s2:begin
                if(din==1)
                    next_state=s3;
                else
                    next_state=s1;
            end
            s3:begin
                if(din==0)
                    next_state=s4;
                else
                    next_state=s3;
            end
            s4:begin
                    next_state=s1;
            end
        endcase
end

reg y;

always@(posedge clk or negedge rst_n)
begin
    if(!rst_n)
        y<=0;
    else if(cur_state==s4 && din==1)
        y<=1;
    else
        y<=0;
end

always@(posedge clk or negedge rst_n)
begin
    if(!rst_n)
        Y<=0;
    else
        Y<=y;
end


endmodule