题解 | #边沿检测#

`timescale 1ns/1ns
module edge_detect(
	input clk,
	input rst_n,
	input a,
	
	output reg rise,
	output reg down
);


reg a_tmp;
always@(posedge clk or negedge rst_n)begin
    if(!rst_n)begin
        a_tmp <= 0;
    end
    else begin
        a_tmp <= a;
    end
end

always@(posedge clk or negedge rst_n)begin
    if(!rst_n)begin
        rise <= 0;
        down <= 0;
    end
    else begin
        case({a_tmp,a})
            2'b01 : begin rise <= 1; end
            2'b10 : begin down <= 1; end
            default : begin rise <= 0; down <= 0; end
        endcase
    end
end






endmodule