题解 | #含有无关项的序列检测#

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input a,
	output reg match
	);
reg [8:0] men;
always@(posedge clk or negedge rst_n)begin
    if(!rst_n)begin
        men <= 0;
    end
    else begin
        men <= {men[6:0],a};
    end
end

always@(posedge clk or negedge rst_n)begin
    if(!rst_n)begin
        match <= 0;
    end
    else if({men[8:6],men[2:0]}==8'h1e)begin
        match <= 1;
    end
    else begin
        match <= 0;
    end
end
endmodule