题解 | #输入序列不连续的序列检测#

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input data,
	input data_valid,
	output reg match
	);
	reg [3:0]a_r;
	always@(posedge clk or negedge rst_n)begin
		if(!rst_n)
			a_r<=4'b0;
		else if(!data_valid)
			a_r<=a_r;
		else
			a_r<={a_r[2:0],data};
	end
	always@(posedge clk or negedge rst_n )begin
		if(!rst_n)
			match <= 0;
		//else if(a_r==4'b0110)
		else if(a_r[2:0]==3'b011 && data==0 && data_valid)
			match <= 1;
		else
			match <= 0;
	end


  
endmodule

题目的testbench有问题，注释掉的条件是正常的题目要求，需要改成匹配到0110的时钟周期立即拉高match信号才可以通过