题解 | #RAM的简单实现#

`timescale 1ns/1ns
module ram_mod(
	input clk,
	input rst_n,
	
	input write_en,
	input [7:0]write_addr,
	input [3:0]write_data,
	
	input read_en,
	input [7:0]read_addr,
	output reg [3:0]read_data
);
	reg [3:0] mem [0:255];

	genvar i;
	generate
		for(i=0;i<128;i=i+1) begin
			always @(posedge clk or negedge rst_n) begin
				if(~rst_n) begin
					mem[i] <= 4'h0;
				end
				else if(write_en && write_addr == i) begin
					mem[i] <= write_data;
				end
			end
		end
	endgenerate

	always @(*) begin
		if(read_en) begin
			if(read_addr == write_addr && write_en) begin
				read_data = write_data;
			end
			else begin
				read_data = mem[read_addr];
			end
		end
		else begin
			read_data = 4'h0;
		end
	end 

endmodule