题解 | #序列检测器（Moore型）#

`timescale 1ns/1ns

module det_moore(
   input                clk   ,
   input                rst_n ,
   input                din   ,
 
   output	reg         Y   
);

parameter IDLE = 5'b00001,
            S1 = 5'b00010,
            S2 = 5'b00100,
            S3 = 5'b01000,
            S4 = 5'b10000;

reg [4:0]   state_curr,
            state_next;

//fsm
always @(posedge clk or negedge rst_n) begin
    if (!rst_n)
        state_curr <= IDLE;

    else
        state_curr <= state_next;
end

always @(*) begin
    case (state_curr)
        IDLE:begin
            if (din)
            state_next <= S1;
            else
            state_next <= IDLE; 
        end

        S1:begin
            if(din)
            state_next <= S2;
            else
            state_next <= IDLE;
        end

        S2:begin
            if (!din) 
            state_next  <= S3;
            else
            state_next <= S2;
        end

        S3:begin
            if (din)
            state_next <= S4;
            else
            state_next <= IDLE; 
        end

        S4:if (din)
            state_next <= S1;
        else
            state_next <= S4;

        default :state_next <= state_curr;
    endcase
end

always @(posedge clk or negedge rst_n) begin
    if (!rst_n) 
        Y <= 1'b0;
    else
        if (state_curr == S4)
            Y <= 1'b1;
        else
            Y <= 1'b0;
end

endmodule