题解 | #非整数倍数据位宽转换8to12#

//注意valid_out的输出与valid_in的判断逻辑有关
`timescale 1ns/1ns

module width_8to12(
	input 				 clk 		,   
	input 			     rst_n		,
	input				 valid_in	,
	input	[7:0]		 data_in	,
 
 	output  reg			 valid_out,
	output  reg [11:0]   data_out
);


reg [1 :0]	cnt			;
reg [7 :0]	data_tempt	;


///cnt
always @ (posedge clk or negedge rst_n)
begin//valid_in期间计数，在0-2之间轮续
	if(!rst_n)
		cnt <= 2'd0	;
	else if(valid_in)	
	begin
		if(cnt == 2'd2)	
			cnt <= 2'd0	;
		else
			cnt <= cnt + 1'b1	;
	end
end


///data_tempt
always @ (posedge clk or negedge rst_n)
begin
    if(!rst_n)
        data_tempt <= 8'd0  ;
    else if(valid_in)
        data_tempt <= data_in   ;
end


///data_out & valid_out
always @ (posedge clk or negedge rst_n)
begin
    if(!rst_n)  begin
        data_out    <= 12'd0;
        valid_out   <= 1'b0 ;
    end
    else    begin
        if(cnt == 2'd1 & valid_in)begin
            valid_out <= 1'b1   ;
            data_out  <= {data_tempt, data_in[7:4]}  ;
        end
        else if(cnt == 2'd2 & valid_in)begin
            valid_out <= 1'b1   ;
            data_out  <= {data_tempt[3:0], data_in}  ;
        end
        else	begin
			valid_out <= 1'b0	;
			data_out  <= data_out	;
		end
    end
end


endmodule