题解 | #任意小数分频#

// 3*8 + 7*9 = 87， 即10个clk_out = 87个clk_in 则平均频率满足分频要求
`timescale 1ns/1ns

module div_M_N(
 input  wire clk_in,
 input  wire rst,
 output wire clk_out
);
parameter M_N = 8'd87; 
parameter c89 = 8'd24; // 8/9时钟切换点
parameter div_e = 5'd8; //偶数周期
parameter div_o = 5'd9; //奇数周期


reg [3 :0]  div_cnt     ;
reg [6 :0]  clk_cnt     ;
reg         clk_out_r   ;

//clk_cnt 持续计数，计到87-1则归零
always @(posedge clk_in or negedge rst) 
begin
    if(!rst)
        clk_cnt <= 7'd0 ;
    else
        clk_cnt <= (clk_cnt == M_N -1'b1) ? 7'd0 : clk_cnt + 1'b1   ;
end

//div_cnt 根据clk_cnt所处区间不同，分频计数值分别取div_e和div_o
always @(posedge clk_in or negedge rst)
begin
    if(!rst)
        div_cnt <= 4'd0 ;
    else    begin
        if(clk_cnt <= c89 -1'b1)
            div_cnt <= (div_cnt == div_e -1'b1) ? 4'd0  : div_cnt + 1'b1    ;
        else if(clk_cnt >= c89)
            div_cnt <= (div_cnt == div_o -1'b1) ? 4'd0  : div_cnt + 1'b1    ;
    end
end

//clk_out_r 分clk_cnt区间对div_o和div_e作出相应翻转
always @(posedge clk_in or negedge rst)
begin
    if(!rst)
        clk_out_r <= 1'b0   ;
    else begin
        if(clk_cnt <= c89 -1'b1)
            clk_out_r <= (div_cnt == 4'd0 || div_cnt == div_e/2) ? ~clk_out_r  : clk_out_r    ;
        else if(clk_cnt >= c89)
            clk_out_r <= (div_cnt == 4'd0 || div_cnt == (div_o - 1'd1)/2) ? ~clk_out_r  : clk_out_r    ;
    end
end

assign clk_out = clk_out_r  ;


endmodule