题解 | #数据串转并电路#

//本题最坑的地方在于data_a到data_b相对计数器是两级逻辑，但是valid_b拉高相对计数器只需要一级逻辑
//这就导致在计数器为5的时候data_a要寄存到缓存寄存器中，而data_b此时直接寄存缓存寄存器时将遗漏一位
//当然牛客网的题目和仿真也很垃圾，鬼知道他的TB给的是哪些数据，想自己仿真都不行
`timescale 1ns/1ns
module s_to_p(
	input 				clk 		,   
	input 				rst_n		,
	input				valid_a		,
	input	 			data_a		,
 
 	output	reg 		ready_a		,
 	output	reg			valid_b		,
	output  reg [5:0] 	data_b
);
reg [2:0] counter;

reg [5:0] data_reg;

always@(posedge clk or negedge rst_n)begin
  if(!rst_n)
    ready_a <= 1'b0;
  else
    ready_a <= 1'b1;
end

always@(posedge clk or negedge rst_n)begin
  if(!rst_n)
    counter <= 1'b0;
  else if(valid_a)begin
    if(counter == 3'd5)
	  counter <= 1'b0;
	else
      counter <= counter + 1'b1;
  end
  else 
    counter <= counter;
end

always@(posedge clk or negedge rst_n)begin
  if(!rst_n)
    data_reg <= 1'b0;
  else if(valid_a)
    data_reg <= {data_a,(data_reg[5:1])};
  else 
    data_reg <= data_reg;
end

always@(posedge clk or negedge rst_n)begin
  if(!rst_n)begin
    data_b <= 1'b0;
	valid_b <= 1'b0;
  end
  else if(counter == 3'd5)begin
    data_b <= {data_a,(data_reg[5:1])};
	valid_b <= 1'b1;
  end
  else begin
    data_b <= data_b;
	valid_b <= 1'b0;
  end
end

endmodule