题解 | #脉冲同步电路#

//49 脉冲同步电路
`timescale 1ns/1ns

module pulse_detect(
	input 				clk_fast	, 
	input 				clk_slow	,   
	input 				rst_n		,
	input				data_in		,

	output  		 	dataout
);

reg data_in_req;
reg data_in_req_f2s_r1;
reg data_in_req_f2s_r2;

reg data_in_req_s2f_r1;
reg data_in_req_s2f_r2;
reg data_out_d;

//脉冲展宽
always@(posedge clk_fast or negedge rst_n)begin
    if(!rst_n)begin
        data_in_req <= 0;
    end
    else if(data_in)begin
        data_in_req <= 1'b1;
    end
    else if(data_in_req_s2f_r2)begin
        data_in_req <= 1'b0;
    end
end
//慢时钟域打两拍同步展宽信号
always@(posedge clk_slow or negedge rst_n)begin
    if(!rst_n)begin
        data_in_req_f2s_r1 <= 0;
        data_in_req_f2s_r2 <= 0;
    end
    else begin
        data_in_req_f2s_r1 <= data_in_req;
        data_in_req_f2s_r2 <= data_in_req_f2s_r1;
    end
end
//打一拍进行上升沿检测，产生慢时钟域脉冲信号
always@(posedge clk_slow or negedge rst_n)begin
    if(!rst_n)begin
        data_out_d <= 0;
    end
    else begin
        data_out_d <= data_in_req_f2s_r2;
    end
end
assign dataout = ~data_out_d & data_in_req_f2s_r2;

//快时钟域打两拍，拉低展宽信号
always@(posedge clk_fast or negedge rst_n)begin
    if(!rst_n)begin
        data_in_req_s2f_r1 <= 0;
        data_in_req_s2f_r2 <= 0;
    end
    else begin
        data_in_req_s2f_r1 <= dataout;
        data_in_req_s2f_r2 <= data_in_req_s2f_r1;
    end
end


endmodule