题解 | #同步FIFO#

`timescale 1ns/1ns
/**********************************RAM************************************/
module dual_port_RAM #(parameter DEPTH = 16,
					   parameter WIDTH = 8)(
	 input wclk
	,input wenc
	,input [$clog2(DEPTH)-1:0] waddr  //深度对2取对数，得到地址的位宽。
	,input [WIDTH-1:0] wdata      	//数据写入
	,input rclk
	,input renc
	,input [$clog2(DEPTH)-1:0] raddr  //深度对2取对数，得到地址的位宽。
	,output reg [WIDTH-1:0] rdata 		//数据输出
);

reg [WIDTH-1:0] RAM_MEM [0:DEPTH-1];

always @(posedge wclk) begin
	if(wenc)
		RAM_MEM[waddr] <= wdata;
end 

always @(posedge rclk) begin
	if(renc)
		rdata <= RAM_MEM[raddr];
end 

endmodule  

/**********************************SFIFO************************************/
module sfifo#(
	parameter	WIDTH = 8,
	parameter 	DEPTH = 16
)(
	input 					clk		, 
	input 					rst_n	,
	input 					winc	,
	input 			 		rinc	,
	input 		[WIDTH-1:0]	wdata	,

	output reg				wfull	,
	output reg				rempty	,
	output wire [WIDTH-1:0]	rdata
);

//读写地址产生
//扩展1位
reg [$clog2(DEPTH):0]   waddr;
reg [$clog2(DEPTH):0]   raddr;

always@(posedge clk or negedge rst_n)begin
    if(!rst_n)begin
        waddr <= 0;
    end
    else if(winc&~wfull)begin
        waddr <= waddr + 1;
    end
end

always@(posedge clk or negedge rst_n)begin
    if(!rst_n)begin
        raddr <= 0;
    end
    else if(rinc&~rempty)begin
        raddr <= raddr + 1;
    end
end

//空满信号标志
/*
assign wfull = (waddr[$clog2(DEPTH)] != raddr[$clog2(DEPTH)]) & (waddr[$clog2(DEPTH)-1:0] == raddr[$clog2(DEPTH)-1:0]) ? 1'b1:1'b0;
assign rempty = waddr == raddr ? 1'b1 : 1'b0;
*/

    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            wfull <= 'd0;
            rempty <= 'd0;
        end
        else begin
            wfull <= waddr == raddr + DEPTH;
            rempty <= waddr == raddr;
        end
    end


//双端口RAM例化

dual_port_RAM
#(
    .DEPTH(16),
    .WIDCH(8)
)u_Dual_part_RAM(
.wclk   (clk),
.wenc   (winc&~wfull),
.waddr  (waddr),
.wdata  (wdata),
.rclk   (clk),
.renc   (rinc&~rempty),
.raddr  (raddr),
.rdata  (rdata)
);


endmodule