题解 | #数据串转并电路#

`timescale 1ns/1ns

module s_to_p(
	input 				clk 		,   
	input 				rst_n		,
	input				valid_a		,
	input	 			data_a		,
 
 	output	reg 		ready_a		,
 	output	reg			valid_b		,
	output  reg [5:0] 	data_b
);

reg [2:0] cnt;
reg valid_b_reg;
reg [5:0] data_b_reg;

always@(posedge clk or negedge rst_n)begin
	if(!rst_n)
		cnt<=0;
	else if(ready_a & cnt==3'd5 & valid_a)
		cnt<=0;
	else if(ready_a & valid_a)
		cnt<=cnt+1;
	else 
		cnt<=cnt;
end

always@(posedge clk or negedge rst_n)begin
	if(!rst_n)
		valid_b_reg<=0;
	else if(cnt==3'd4 & ready_a & valid_a)
		valid_b_reg<=1;
	else
	    valid_b_reg<=0;

end

always@(posedge clk or negedge rst_n)begin
	if(!rst_n)
		valid_b<=0;
	else begin
		valid_b<=valid_b_reg;
	end
end

always@(posedge clk or negedge rst_n)begin
	if(!rst_n)
		data_b_reg<=0;
	else if(ready_a & valid_a)
		data_b_reg<={data_a,data_b_reg[5:1]};
	else
		data_b_reg<=data_b_reg;
end
always@(posedge clk or negedge rst_n)begin
	if(!rst_n)
		ready_a<=0;
	else 
		ready_a<=1;
end

always@(posedge clk or negedge rst_n)begin
	if(!rst_n)
		data_b<=0;
	else if(valid_b_reg)
		data_b<={data_a,data_b_reg[5:1]};
	else
		data_b<=data_b;
end

endmodule