题解 | #数据串转并电路#

`timescale 1ns/1ns

module s_to_p(
	input 				clk 		,   
	input 				rst_n		,
	input				valid_a		,
	input	 			data_a		,
 
 	output	reg 		ready_a		,
 	output	reg			valid_b		,
	output  reg [5:0] 	data_b
);

	reg [5:0]	temp;
	reg [2:0]	cnt;

	always@(posedge clk,negedge rst_n)begin
		if(!rst_n)
			temp <= 'd0;
		else if(valid_a && ready_a)
			temp <= {data_a,temp[5:1]};
	end

	always@(posedge clk,negedge rst_n)begin
		if(!rst_n)
			ready_a <= 'd0;
		else
			ready_a <= 'd1;
	end

	always@(posedge clk,negedge rst_n)begin
		if(!rst_n)
			cnt <= 'd0;
		else if(valid_a && ready_a)begin
			if(cnt == 'd5)
				cnt <= 'd0;
			else
				cnt <= cnt + 'd1;
		end
	end

	always@(posedge clk,negedge rst_n)begin
		if(!rst_n)
			valid_b <= 'd0;
		else if(cnt == 'd5 && valid_a && ready_a)
			valid_b <= 'd1;
		else
			valid_b <= 'd0;
	end

	always@(posedge clk,negedge rst_n)begin
		if(!rst_n)
			data_b <= 'd0;
		else if( cnt == 'd5 && valid_a && ready_a)
			data_b <= {data_a,temp[5:1]};
	end



endmodule