题解 | #序列发生器#

`timescale 1ns/1ns

module sequence_generator(
	input clk,
	input rst_n,
	output reg data
	);
//一直移位就好了
reg [5:0] data_reg;
always@(posedge clk or negedge rst_n)begin
  if(!rst_n) begin
    data <= 1'd0;
    data_reg <= 6'b001011;
  end
  else begin
    data_reg <= {data_reg[4:0],data_reg[5]};
    data <= data_reg[5];//一直提示有错误，原来是这里把data写成data_reg了
  end
end
endmodule