题解 | #使用子模块实现三输入数的大小比较#

`timescale 1ns/1ns
module main_mod(
	input clk,
	input rst_n,
	input [7:0]a,
	input [7:0]b,
	input [7:0]c,
	
	output [7:0]d
);
    wire [7:0]temp1;
	wire [7:0]temp2;
	compare com1(
		.clk(clk),
		.rst_n(rst_n),
		.a(a),
		.b(b),
		.out(temp1)
	);
		compare com2(
		.clk(clk),
		.rst_n(rst_n),
		.a(a),
		.b(c),
		.out(temp2)
	);
		compare com3(
		.clk(clk),
		.rst_n(rst_n),
		.a(temp1),
		.b(temp2),
		.out(d)
	);
endmodule

module compare(
	input clk,
	input rst_n,
	input [7:0]a,
	input [7:0]b,

	output [7:0]out
);
   reg[7:0]com;
   always@(posedge clk or negedge rst_n)
   if(!rst_n)
   com<=0;
   else begin
	com<=(a>=b)?b:a;
   end
   assign out=com;
endmodule