题解 | #并串转换#

`timescale 1ns/1ns
module huawei5(
	input wire clk  ,
	input wire rst  ,
	input wire [3:0]d ,

	output wire valid_in,
	output wire dout
	);

reg[3:0]temp;
reg vaild_temp;
reg [1:0]point=2'b00;

always@(posedge clk or negedge rst)
if(!rst)begin
    vaild_temp<=0;
    temp<=0;
end 
else begin
point<=point+1'b1;

if(point==2'b11)begin
        vaild_temp<=1;
        temp<=d;
        end
else    vaild_temp<=0;

end	

assign dout=temp[3-point];
assign valid_in=vaild_temp;

endmodule