题解 | #不重叠序列检测#

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input data,
	output reg match,
	output reg not_match
	);

reg [3:0] state;
reg [3:0] nstate;
parameter S0 = 4'b0000;
parameter S1 = 4'b0001;
parameter S2 = 4'b0010;
parameter S3 = 4'b0011;
parameter S4 = 4'b0100;
parameter S5 = 4'b0101;
parameter S6 = 4'b0110;
parameter S7 = 4'b0111;
parameter S8 = 4'b1000;
parameter S9 = 4'b1001;
reg flag;
reg nflag;
reg m;
reg [2:0]cnt;
parameter max=6-1;
// 计时
always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        cnt <= S1;  // 初始化状态
    end else if(cnt>=max)
        cnt<=3'b0;
		else 
		cnt<=cnt+1;
    end

// 状态寄存器更新逻辑
always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        state <= S1;  // 初始化状态
    end else begin
        state <= nstate;
    end
end

// 状态转移逻辑
always @(*) begin
    nstate = state;  // 默认不变状态
    flag = 0;  // 默认情况下不设置flag

    case (state)
        S1: begin
            if (data == 0)
                nstate = S2;
            else
                nstate = S0;
        end
        S2: begin
            if (data == 1)
                nstate = S3;
            else
                nstate = S0;
        end
        S3: begin
            if (data == 1)
                nstate = S4;
            else
                nstate = S0;
        end
        S4: begin
            if (data == 1 )
                nstate = S5;
            else
                nstate = S0;
        end
        S5: begin
            if (data == 0)
                nstate = S6;
            else
                nstate = S0;
        end
        S6: begin
            if (data == 0 ) begin
                nstate = S1;
				flag=1;
			end else
                nstate = S0;
        end
        
        
        S0: begin
            nflag=1;
			if(cnt==max)
			nstate=S1;
			else
			nstate=S0;
        end
		/*: begin
            if (a == 0) begin
                nstate = S9;
                
            end else begin
                nstate = S1;
            end
        end
		S9: begin
            
                flag=1;
                nstate = S1;
            end*/
    
    endcase
end

// 输出逻辑
always @(posedge clk or negedge rst_n) begin
    if (!rst_n)
        not_match <= 1'b0;
     else  
       not_match <= m;
     
		
    
end
//打一拍符合时序

always @(posedge clk or negedge rst_n) begin
   if (!rst_n) 
      m <= 1'b0;
     else if (nflag && cnt==max)
       m <= nflag;
  
end
always @(posedge clk or negedge rst_n) begin
   if (!rst_n) begin
      match <= 1'b0;
    end else begin
       match <= flag;
    end
end
endmodule