题解 | #4bit超前进位加法器电路#

`timescale 1ns/1ns

module lca_4(
	input		[3:0]       A_in  ,
	input	    [3:0]		B_in  ,
    input                   C_1   ,
 
 	output	 wire			CO    ,
	output   wire [3:0]	    S
);

and g0and(g0,A_in[0],B_in[0]),
    g1and(g1,A_in[1],B_in[1]),
	g2and(g2,A_in[2],B_in[2]),
	g3and(g3,A_in[3],B_in[3]),
	p0and(p0and,p0,C_1),
	p1and(p1and,p1,c00),
	p2and(p2and,p2,c01),
	p3and(p3and,p3,c02);



xor p0xor(p0,A_in[0],B_in[0]),
    p1xor(p1,A_in[1],B_in[1]),
	p2xor(p2,A_in[2],B_in[2]),
	p3xor(p3,A_in[3],B_in[3]),
	s0(S[0],p0,C_1),
	s1(S[1],p1,c00),
	s2(S[2],p2,c01),
	s3(S[3],p3,c02);

or c0or(c00,g0,p0and),
   c1or(c01,g1,p1and),
   c2or(c02,g2,p2and),
   c3or(CO,g3,p3and);

endmodule