题解 | #不重叠序列检测#

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input data,
	output reg match,
	output reg not_match
	);

	localparam s0=3'b001;
	localparam s1=3'b010;
	localparam s2=3'b011;
	localparam s3=3'b100;
	localparam s4=3'b101;
	localparam s5=3'b110;
	localparam s6=3'b111;

	reg[2:0]state,next;
	reg[5:0]temp;

	always@(posedge clk or negedge rst_n)
	if(!rst_n)begin
		state<=s0;
		match<=0;
		not_match<=0;
	end else begin
		state<=next;
	end

	always@(*)
	case(state)
	s0:begin
		next=s1;
		match=0;
		not_match=0;
		temp[0]=data;
	end
	s1:begin
		next=s2;
		match=0;
		not_match=0;
		temp[1]=data;
	end
	s2:begin
		next=s3;
		match=0;
		not_match=0;
		temp[2]=data;
	end
	s3:begin
		next=s4;
		match=0;
		not_match=0;
		temp[3]=data;
	end
	s4:begin
		next=s5;
		match=0;
		not_match=0;
		temp[4]=data;
	end
	s5:begin
		next=s6;
		match=0;
		not_match=0;
		temp[5]=data;
	end
	s6:if(temp==6'b001110)begin
		match=1;
		not_match=0;
		next=s1;
		temp[0]=data;
	end else begin
		match=0;
		not_match=1;
		next=s1;
		temp[0]=data;
	end
	endcase


endmodule