题解 | #并串转换#

`timescale 1ns/1ns
module huawei5(
	input wire clk  ,
	input wire rst  ,
	input wire [3:0]d ,
	output wire valid_in ,
	output wire dout
	);

//*************code***********//
//左移
reg valid;
reg [3:0] data;
reg [1:0] cnt;
 always@(posedge clk or negedge rst) begin
  if(!rst) 
     cnt <= 0;
   else 
     cnt <= cnt + 1'b1;
 end

 always@(posedge clk or negedge rst) begin
  if(!rst) begin
	 valid <= 0;
	 data <= 0;
  end
  else if(cnt==2'd3) begin
      valid <= 1'b1;
      data  <= d;
  end
  else begin
    valid <= 0;
	data <= data;
	data <= data << 1;
	//data <= {data[2:0],data[3]};
  end
  end
  assign valid_in = valid;
  assign dout = data[3];
//*************code***********//

endmodule