题解 | #输入序列连续的序列检测#

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input a,
	output reg match
	);

reg [3:0] curr_state;
reg [3:0] next_state;
reg       match_t;


parameter IDLE = 4'b0000;
parameter M1   = 4'b0001;
parameter M2   = 4'b0011;
parameter M3   = 4'b0111;
parameter M4   = 4'b1111;
parameter M5   = 4'b1110;
parameter M6   = 4'b1100;
parameter M7   = 4'b1000;
parameter M8   = 4'b1010;

always @(posedge clk or negedge rst_n)begin
	if(rst_n == 1'b0)
	curr_state <= IDLE;
	else
	curr_state <= next_state;
end
  
always @(*)begin
	case(curr_state)
	IDLE: 
	    if(a == 1'b0)
		    next_state = M1;
		else
		    next_state = IDLE;

	M1:
	    if(a == 1'b1)
		    next_state = M2;
		else
		    next_state = M1;

	M2:
	    if(a == 1'b1)
		    next_state = M3;
		else
		    next_state = M1;
    M3:
	    if(a == 1'b1)
		    next_state = M4;
		else
		    next_state = M1;
	M4:
	    if(a == 1'b0)
		   next_state = M5;
		else
		   next_state = IDLE;
	M5: 
	    if(a == 1'b0)
		   next_state = M6;
		else
		   next_state = M2;
	M6:
	    if(a == 1'b0)
		   next_state = M7;
		else
		   next_state = M2;
    M7:
	    if(a == 1'b1)
		   next_state = M8;
		else
		   next_state = M1;
    M8:
	    if(a == 1'b0)
		   next_state = M1;
		else
		   next_state = M3;

	endcase
end  


always@(posedge clk or negedge rst_n)begin
	if(rst_n == 1'b0)begin
		match_t <= 0;
	end
	else if(next_state == M8)begin
		match_t <= 1'b1;
	end
	else begin
		match_t <= 1'b0;
	end
end

always@(posedge clk or negedge rst_n)begin
	if(rst_n == 1'b0)
	   match <= 0;
	else
	   match <= match_t;
end
endmodule