题解 | #输入序列不连续的序列检测#

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input data,
	input data_valid,
	output reg match
	);

reg [2:0] curr_st;
reg [2:0] next_st;
parameter M0 = 3'b0;
parameter M1 = 3'b01;
parameter M2 = 3'b10;
parameter M3 = 3'b11;
parameter M4 = 3'b100;

always @(posedge clk or negedge rst_n)begin
	if(rst_n == 1'b0)
	   curr_st <= M0;
	else
	   curr_st <= next_st;
end

always@(*)begin
	case(curr_st)
	M0: 
	    if(data_valid)begin
		   if(data == 1'b0) next_st = M1;
		   else  next_st =  M0;
		end
		else
		   next_st = M0;

	M1:
	    if(data_valid)begin
			if(data == 1'b1) next_st = M2;
			else next_st = M1;
		end
		else
		    next_st = M1;
	M2: 
	    if(data_valid)begin
			if(data == 1'b1) next_st = M3;
			else next_st = M1;
		end
		else
		   next_st = M2;

	M3: 
	    if(data_valid)begin
			if(data == 1'b0) next_st = M4;
			else  next_st = M0;
		end
		else
		    next_st= M3;
	M4:
	    if(data_valid)begin
			if(data == 1'b0) next_st = M1;
			else  next_st = M0;
		end
		else
		   next_st = M0;

	endcase
end

always @(posedge clk or negedge rst_n)begin
	if(rst_n == 1'b0)
	   match <= 0;
	else if(next_st == M4)
	   match <= 1;
	else
	   match <= 0;
end
endmodule