题解 | 占空比50%的奇数分频

`timescale 1ns/1ns

module odo_div_or
#(parameter N = 7)//N=7七分频
(
    input wire rst,
    input wire clk_in,
    output wire clk_out7
);

reg [3:0] cnt;

always@(posedge clk_in or negedge rst)begin
    if(!rst)begin
        cnt <= 'b0;
    end
    else if (cnt == N-1)begin//分频系数减到1
        cnt <= 'b0;
    end
    else begin
        cnt <= cnt + 1'b1;
    end
end

reg clkp;//用于生成上升沿触发的时钟信号
always@(posedge clk_in or negedge rst)begin
    if(!rst)begin
        clkp <= 'b0;
    end
    else if(cnt == (N>>1))begin//如果cnt等于N/2
        clkp <= 1;
    end
    else if(cnt == N-1)begin
        clkp <= 0;
    end
end

reg clkn;
always@(negedge clk_in or negedge rst)begin
    if(!rst)begin
        clkn <= 1'b0;
    end
    else if(cnt == (N>>1))begin//如果cnt等于N/2
        clkn <= 1;
    end
    else if(cnt == N-1)begin
        clkn <= 0;
    end
end

assign clk_out7= clkp | clkn;

endmodule