题解 | 非整数倍数据位宽转换8to12

`timescale 1ns/1ns

module width_8to12(
	input 				   clk 		,   
	input 			      rst_n		,
	input				      valid_in	,
	input	[7:0]			   data_in	,
 
 	output  reg			   valid_out,
	output  reg [11:0]   data_out
);
reg [1:0] data_in_cnt;
reg [7:0] data_in_reg;
always@(posedge clk or negedge rst_n)
if(!rst_n)
  data_in_cnt <= 0;
else if(valid_in)
  data_in_cnt <= (data_in_cnt==2'd2)?0:(data_in_cnt +1'b1);

always@(posedge clk or negedge rst_n)
if(!rst_n) begin
	data_in_reg <= 0;
	data_out <= 0;
	valid_out <= 0;
end
else if(valid_in)begin
	data_in_reg <= data_in;
	if(data_in_cnt==2'd1)begin
		data_out <= {data_in_reg,data_in[7:4]};
		valid_out <= 1;
	end
	else if(data_in_cnt==2'd2)begin
		data_out <= {data_in_reg[3:0],data_in};
		valid_out <= 1;
	end
end
	else 
		valid_out <= 0;

endmodule