题解 | 整数倍数据位宽转换8to16

`timescale 1ns/1ns

module width_8to16(
	input 				   clk 		,   
	input 				   rst_n		,
	input				      valid_in	,
	input	   [7:0]		   data_in	,
 
 	output	reg			valid_out,
	output   reg [15:0]	data_out
);
reg [1:0] data_cnt;
reg [7:0] data_in_reg;
always@(posedge clk or negedge rst_n)
if(!rst_n)
  data_cnt <= 0;
else if(valid_in)
  data_cnt <= (data_cnt ==2'd1)?0:(data_cnt + 1);

always@(posedge clk or negedge rst_n)
if(!rst_n)begin
	data_in_reg <= 0;
	data_out <= 0;
	valid_out <= 0;
end
else if(valid_in)begin
	data_in_reg <= data_in;
	if(data_cnt==1)begin
		data_out <= {data_in_reg,data_in};
		valid_out <= 1;
	end
	else begin
		data_out <= data_out; 
		valid_out <= 0;
	end
end
else begin
data_in_reg <= data_in_reg;
valid_out <= 0;
end
endmodule