题解 | 状态机-非重叠的序列检测

`timescale 1ns/1ns

module sequence_test1(
	input wire clk  ,
	input wire rst  ,
	input wire data ,
	output reg flag
);
//*************code***********//
//寄存器输出且同步输出结果-->mealy型
//法一：三段式状态机
reg [2:0] current_state,next_state;
always@(posedge clk or negedge rst)
if(!rst)
   current_state <= 3'd0;
else 
   current_state <= next_state;

always@(*)
  if(!rst)
    next_state <= 3'd0;
  else begin
	case(current_state)
	3'd0:next_state <= data ? 3'd1 :3'd0;
	3'd1:next_state <= (data==0) ? 3'd2 :3'd1;
	3'd2:next_state <= data ? 3'd3 :3'd0;
	3'd3:next_state <= data ? 3'd4 :3'd2;
	3'd4:next_state <= data ? 3'd0 :3'd2;
	// 3'd5:next_state <= data ? 3'd1 :3'd0;//moore型，多一拍
    default:next_state <= 3'd0;
	endcase
  end

always@(posedge clk or negedge rst)
if(!rst)
  flag <= 0;
// else if(current_state==3'd5)//moore型
else if(current_state==3'd4 && data)//mealy型，寄存器输出且同步输出结果
  flag <= 1;
else
  flag <= 0;
//*************code***********//
//法二：移位寄存器：
// reg [4:0] data_reg;
// always@(posedge clk or negedge rst)
// if(!rst)
//   data_reg <= 0;
// else if(data_reg[4:0]==5'b10111)
//   data_reg <= 0;//非重叠检测
// else
//   data_reg <= {data_reg[3:0],data};

// always@(posedge clk or negedge rst)
// if(!rst)
//   flag <= 0;
// else if({data_reg[3:0],data}==5'b10111)//寄存器输出且同步输出结果
//   flag <= 1;
// else 
//   flag <= 0;

endmodule