题解 | 时钟分频（偶数）

`timescale 1ns/1ns

module even_div
    (
    input     wire rst ,
    input     wire clk_in,
    output    wire clk_out2,
    output    wire clk_out4,
    output    wire clk_out8
    );
//*************code***********//
//法1：clk_out_8:1, 1, 1, 1 ,0 ,0 ,0 ,0
//法1：clk_out_4:1, 1, 0, 0 ,1 ,1 ,0 ,0
//法1：clk_out_2:1, 0, 1, 0 ,1 ,0 ,1 ,0
//可以看到是一个减法器
// reg [2:0] cnt;
// always@(posedge clk_in or negedge rst)
// if(!rst)
//   cnt <= 0;
// else 
//   cnt <= cnt - 1;

// assign {clk_out8,clk_out4,clk_out2}=cnt;

//*************code***********//
reg clk_out2_r;
reg clk_out4_r;
reg clk_out8_r;
always@(posedge clk_in or negedge rst)
if(!rst)
  clk_out2_r <= 0;
else
  clk_out2_r <= ~clk_out2_r;

always@(posedge clk_out2 or negedge rst)
if(!rst)
  clk_out4_r <= 0;
else
  clk_out4_r <= ~clk_out4_r;

always@(posedge clk_out4 or negedge rst)
if(!rst)
  clk_out8_r <= 0;
else
  clk_out8_r <= ~clk_out8_r;

assign clk_out2=clk_out2_r;
assign clk_out4=clk_out4_r;
assign clk_out8=clk_out8_r;


endmodule