题解 | 加减计数器

`timescale 1ns/1ns

module count_module(
	input clk,
	input rst_n,
	input mode,
	output reg [3:0]number,
	output reg zero
	);
//
reg [3:0] number0;
always@(posedge clk or negedge rst_n)
if(!rst_n)
  number <= 0;
else
  number <= number0;

always@(posedge clk or negedge rst_n)
if(!rst_n)
  number0 <= 0;
else if(mode)//递增
  number0 <= (number0==4'd9) ? 0 : (number0 + 1);
else 
  number0 <= (number0==4'd0) ? 9 : (number0 - 1);

always@(posedge clk or negedge rst_n)
if(!rst_n)
  zero <= 0;
else 
 zero <= (number0==0) ? 1 : 0;
 
endmodule