题解 | 异步复位的串联T触发器

`timescale 1ns/1ns
module Tff_2 (
input wire data, clk, rst,
output reg q  
);
//*************code***********//

reg data_1;

always @ (posedge clk or negedge rst) begin
    if (rst==0)
        data_1 <= 0;
    else if (data)
        data_1 <= ~data_1;
    else
        data_1 <= data_1;
end

always @ (posedge clk or negedge rst) begin
    if (rst==0)
        q <= 0;
    else if (data_1)
        q <= ~q;
    else
        q <= q;
end



//*************code***********//
endmodule