题解 | 占空比50%的奇数分频

`timescale 1ns/1ns

module odo_div_or
   (
    input    wire  rst ,
    input    wire  clk_in,
    output   wire  clk_out7
    );

//*************code***********//
    reg [2:0]   cnt_pos;
    reg [2:0]   cnt_neg;
    wire clk_pos;
    wire clk_neg;

    always @(posedge clk_in or negedge rst) begin
        if (!rst) begin
            cnt_pos <= 'b000;
        end
        else if (cnt_pos == 'd6) begin
            cnt_pos <= 'b000; // Reset counter after reaching 6
        end
        else begin
            cnt_pos <= cnt_pos + 1'b1; // Increment counter on positive edge
        end
    end

    always @(negedge clk_in or negedge rst) begin
        if (!rst) begin
            cnt_neg <= 'b000;
        end
        else if (cnt_neg == 'd6) begin
            cnt_neg <= 'b000; // Reset counter after reaching 6
        end
        else begin
            cnt_neg <= cnt_neg + 1'b1; // Increment counter on negative edge
        end
    end

    assign clk_pos = (cnt_pos < 'd4) ? 1'b0 : 1'b1; // Set clk_pos high when counter reaches 6
    assign clk_neg = (cnt_neg < 'd4) ? 1'b0 : 1'b1; // Set clk_neg high when counter reaches 6
    assign clk_out7 = clk_pos | clk_neg; // Output clock is the OR of both clocks
//*************code***********//
endmodule