题解 | 位拆分与运算

`timescale 1ns/1ns

module data_cal(
input clk,
input rst,
input [15:0]d,
input [1:0]sel,

output [4:0]out,
output validout
);
//*************code***********//

reg [4:0] out_reg;
reg validout_reg;
reg [15:0] d_latch;

always @(*) begin
    case (sel)
        0: begin
            out_reg = 5'd0;
            validout_reg = 1'b0;
            d_latch = d;
        end
        1: begin
            out_reg = d_latch[3:0] + d_latch[7:4];
            validout_reg = 1'b1;
        end
        2: begin
            out_reg = d_latch[3:0] + d_latch[11:8];
            validout_reg = 1'b1;
        end
        3: begin
            out_reg = d_latch[3:0] + d_latch[15:12];
            validout_reg = 1'b1;
        end
    endcase
end

assign out = out_reg;
assign validout = validout_reg;

//*************code***********//
endmodule