题解 | #移位运算与乘法#

`timescale 1ns/1ns
module multi_sel(
input [7:0]d ,
input clk,
input rst,
output reg input_grant,
output reg [10:0]out
);

reg[1:0]   state;
reg[7:0]   d1;

always@ (posedge clk or negedge rst) begin
   if(~rst) begin
   input_grant <= 0; out <= 0; state <= 0; d1 <= 0;
   end
   else begin
     if (input_grant == 1) 
     input_grant <= 0;
     else input_grant <= input_grant;
       case(state)
             0://d乘1,用d1将d的值锁存进去
             begin
             out <= d;
             d1 <= d;
             input_grant <= 1;
             state <= 1;
             end
             
             1://d乘3
             begin
             out <= d1 + {d1,1'b0};
             state <= 2;
             end
             
             2://d乘7
             begin
             out <= d1 + {d1,1'b0} + {d1,2'b00};
             state <= 3;
             end
             
             3://d乘8
             begin
             out <= {d1,3'b000};
             state <= 0;
             end
          
       endcase
   end

end


endmodule