题解 | #多bit MUX同步器#

`timescale 1ns/1ns

module mux( input clk_a , input clk_b ,
input arstn , input brstn , input [3:0] data_in , input data_en ,

output reg  [3:0] 	dataout

); reg [3:0]qa_data; reg qa_en; reg qb_en_1,qb_en_2;

always @(posedge clk_a or negedge arstn)begin
    if(~arstn)begin
        qa_en<=0;qa_data<=0;
    end
    else begin
        qa_en<=data_en;
        qa_data<=data_in;
    end
end

always @(posedge clk_b or negedge brstn)begin
    if(~brstn)begin
        qb_en_1<=0;qb_en_2<=0;
    end
    else begin
        qb_en_1<=qa_en;
        qb_en_2<=qb_en_1;
    end
end


always @(posedge clk_b or negedge brstn)begin
    if(~brstn)begin
        dataout<=0;
    end
    else if(qb_en_2==1)begin
        dataout<=qa_data;
    end
    else begin
        dataout<=dataout;
    end
end

endmodule