题解 | #RAM的简单实现#
RAM的简单实现
https://www.nowcoder.com/practice/2c17c36120d0425289cfac0855c28796
`timescale 1ns/1ns module ram_mod( input clk, input rst_n, input write_en, input [7:0]write_addr, input [3:0]write_data, input read_en, input [7:0]read_addr, output reg [3:0]read_data ); reg [3:0] mem [0:255]; integer i; always@(posedge clk or negedge rst_n) begin if(!rst_n) begin for(i=0;i<=255;i=i+1) begin mem[i] <= 'd0; end end else begin mem[write_addr] <= write_en?write_data:mem[write_addr]; end end always@(posedge clk or negedge rst_n) begin if(!rst_n) begin read_data <= 'd0; end else begin read_data <= read_en?mem[read_addr]:'d0; end end endmodule
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