题解 | #序列检测器（Moore型）#

`timescale 1ns/1ns

module det_moore(
   input                clk   ,
   input                rst_n ,
   input                din   ,
 
   output	reg         Y   
);

    parameter idle = 5'b00001,
              s0 = 5'b00010,
              s1 = 5'b00100,
              s2 = 5'b01000,
              s3 = 5'b10000;
    
    reg [4:0] cur_st,nxt_st;

    always @(posedge clk or negedge rst_n) begin
        if(rst_n == 1'b0)
            cur_st <= idle;
        else
            cur_st <= nxt_st;
    end

    always @(*)begin
        case(cur_st)
            idle:begin
                if(din == 1'b1)
                    nxt_st <= s0;
                else
                    nxt_st <= idle;
            end
            s0: begin
                if(din == 1'b1)
                    nxt_st <= s1;
                else
                    nxt_st <= idle;
            end
            s1:begin
                if(din == 1'b0)
                    nxt_st <= s2;
                else
                    nxt_st <= s1;
            end
            s2:begin
                if(din == 1'b1)
                    nxt_st <= s3;
                else
                    nxt_st <= idle;
            end
            s3:begin
                if(din == 1'b0)
                    nxt_st <= idle;
                else
                    nxt_st <= s0;
            end

        endcase
    end

    always @(posedge clk or negedge rst_n) begin
        if(rst_n == 1'b0)
            Y <= 1'b0;
        else if(cur_st == s3)
            Y <= 1'b1;
        else
            Y <= 1'b0;
    end
endmodule