题解 | #异步复位的串联T触发器#

`timescale 1ns/1ns
module Tff_2 (
input wire data, clk, rst,
output reg q  
);

reg q1;

//*************code***********//
always@(posedge clk or negedge rst)

if(~rst) begin
    q1 <= 1'b0;
    q  <= 1'b0;
end
else begin
    if(data) begin
        q1 <= !q1;
    end
    if(q1) begin
        q <= !q;
    end

end


//*************code***********//
endmodule

`timescale 1ns/1ns



module testbench();
	reg clk=0;
	always #5 clk = ~clk;  // Create clock with period=10
// A testbench
    reg rst,data;
    initial begin
      rst = 0;data=0;
      #60 data = 1;
      #60 data = 0;
      #60 data = 1;
      $finish(0); 
    end

    
 Tff_2 u1(.data(data),
          .rst(rst),
          .clk(clk),
          .q(q)
          );   

//end    
  initial begin
    $dumpfile("out.vcd");
    $dumpvars(0, testbench);
end  
    
endmodule

`timescale 1ns/1ns
module Tff_2 (
input wire data, clk, rst,
output reg q  
);
//*************code***********//
    reg data_1;
    always @ (posedge clk or negedge rst) begin
        if (!rst)
            data_1 <= 1'b0;
        else
            data_1 <= data ^ data_1 ;
    end
    
    always @ (posedge clk or negedge rst) begin
        if (!rst)
            q <= 1'b0;
        else
            q <= data_1 ^ q;
    end

//*************code***********//
endmodule

公式法直接使用Qn+1=Q^T，第二个寄存器根据前一个寄存器的值是否为正